1. Field of the Invention
The invention relates in general to a memory and a reading method thereof, and more particularly to a memory and a reading method thereof capable of enhancing the reading performance.
2. Description of the Related Art
NAND memories are widely applied to various data storage occasions. FIG. 1 (Prior Art) is a partial circuit diagram showing a conventional NAND memory 100. Referring to FIG. 1, the NAND memory 100 includes multiple columns of memory cells, such as the non-limitative three columns of memory cells shown in FIG. 1. First ends of the columns of memory cells are respectively coupled to corresponding bit lines BL1 to BL3, and second ends of the columns of memory cells are coupled to a source line SL. If each column of memory cells includes 32 memory cells, the 32 memory cells are respectively coupled to corresponding word lines WL0 to WL31.
In a conventional memory reading method, the source line SL is substantially coupled to a ground voltage GND, and the source line SL substantially has resistors R1, R2 and R3. Illustrations will be made by taking the memory cell 110 as an example. If the memory cell 110 is programmed first while the other memory cells 120 and 130 are still being the low-threshold status, the high cell current of the memory cells 120 and 130 will charge the source-line resistors R1 and R2 during the program-verify phase, so the voltage of node A will be charged up. As a result, the higher voltage of node A will suppress the cell current of the memory cell 110 since the cell current is proportional to the voltage different between word line (WL0) and source line. That is to say that the cell current I1 might be small enough to pass the program-verify of the memory cell 110, however, this is not because the threshold voltage of the memory cell 110 is programmed high enough, but is because the voltage of source-side of the memory cell 110 is too high which is affected by the other memory cells 120 and 130. As a sequence, if the memory cell of 120 and 130 are programmed later during other programming phase, the cell currents I2 and I3 will become small after the memory cells 120 and 130 pass the program-verify phase of them. Consequently, if a read operation is executed to the memory cell 110, the cell current I1 of the memory cell 110 will not as small as being treated as a high-threshold voltage cell since the enough high threshold voltage of the memory cell 110 during previous programming phase is a false appearance. The memory cell 110 never be programmed actually to a high-threshold voltage cell.
In addition, when the memory cell 110 is finished the program operation, the cell current of it might be as large as “1” cell or as small as “0” cell depending on the program-pattern. However, if any program operation is executed latter to the memory cells 140 and 150 which are belonged to the same string of the memory cell 110, the cell current I1 of the memory 110 will be changed smaller because the memory cells 140 and 150 will become a larger series-connected resister.